An effective work/research proposal consists of the following elements:
ü Setting of work proposal工作提案建構 : 你工作提案的主題是什麼? 你的讀者可以明瞭工作提案的內容嗎?
ü Work problem工作問題 : 你的工作提案裡有你試著要解決或是想更進一步瞭解的問題嗎?
ü Quantitative specification of problem 問題的量化 : 你要如何量化問題來讓你的讀者明白之前文獻研究所遇到的量化限制 ?
ü Importance of problem問題的中心 : 如果問題沒被解決或是充分瞭解, 這對工作提案的讀者會有多大的負面衝擊?
ü Work objective工作目標 : 工作提案的目標 ?
ü Methodology to achieve objective 達成目標的方法 : 你的計劃中達成目標的步驟?
ü Anticipated results希望的結果 : 你希望達成的結果?
ü Contribution to field領域的貢獻: 你的提案對相關工作領域的貢獻?
Read the following work proposal from Writing Effective Work Proposals by Ted Knoy for an electrical engineering-related (統計相關分類) project:
As IC designs become increasingly complicated and larger,
[ ( xxiv )
hardware emulation is essential for their verification. However,
] [
emulators such as our emulation solution are too expensive and
( iv )
too slow. A Quickturn emulator costs more than a million US
] [ ( xx )
dollars and only works below 1 MHz, which is markedly lower
than the frequency required in newly developed devices. Such a
high cost prevents us from verifying the designs of platforms,
( viii )
and the low speed makes testing difficult and the results
unrealistic, because most devices, which are designed for
66MHz, 100MHz and 133MHz systems, cannot function normally
in the 1MHz environment. Moreover, testing in an emulator
takes an extremely long time, such that a benchmark that
requires 20 minutes in a real system requires 24 hours to
complete in an emulated one.
]
Based on the above, we should develop an emulation method,
[ ( xvi )
costing less and performing more efficiently than conventional
methods. To do so, appropriate types of FPGA, for example,
] [ ( xxxvi )
Virtex E of Xilinx or APEX of Altera, with a retail value of
around US$10,000, can be selected according to size and speed
requirements, to emulate an actual chip. An FPGA synthesis tool,
for example, FPGA compiler or Synplify PRO, can then be
adopted to map the design net-list into a edif file for FPGA.
Next, software for placing and routing FPGA can be employed to
construct an emulation database in FPGA. Additionally, timing
constraints can be established to enhance the emulation.
Moreover, the database can be downloaded into FPGA to initiate
emulation and debug new designs As anticipated, the proposed
method can reduce the costs and time of developing a 10MHz
( xxviii )
frequency by 95%, whereas the conventional method can only be
used at a frequency of 1MHz. The proposed method can
] [ ( xxxii )
reduce testing time, include new devices that cannot function at
1MHz, and allow our company to verify the design with numerous
platforms.
Match the parts of a work proposal with the sentences in the above proposal.
1. Work objective工作目標 in the above proposal can be found in
A. viii
B. xxiv
C. xvi
2. Setting of work proposal工作提案建構 in the above proposal can be found in
A. xxxii
C. viii
3. Importance of problem問題的中心 in the above proposal can be found in
A. xx
B. viii
C. xxxvi
4. Quantitative specification of problem 問題的量化 in the above proposal can be found in
B. xxxii
C. xxiv
5. Methodology to achieve objective 達成目標的方法 in the above proposal can be found in
B. xxviii
6. Work problem工作問題 in the above proposal can be found in
A. xxviii
B. iv
C. xx
7. Contribution to field領域的貢獻 in the above proposal can be found in
B. xxxvi
C. xxxii
8. Anticipated results希望的結果 in the above proposal can be found in
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